1. Technical Field
The present invention relates to a printed circuit board, and more particularly, to a printed circuit board that has coplanar LC balance by differentiating the widths of signal wirings that can be used in semiconductor packages and module boards, and also as a mother board.
2. Description of the Related Art
A developing trend in semiconductor devices and consumer electronics including the same is the pursuit of higher speed, higher performance and smaller size based on a high degree of integration. To achieve high speed, the quality of digital signals on a communication channel must be high. Further, a minimum amount of skew is desired in communication channels having the same function among several communication channels in the devices. As used here, skew refers to a difference in signal transfer delay time generated in communication channels having the same function.
To minimize skew in semiconductor devices and consumer electronics, an interconnect wiring formed by communication channels and pins in the devices should be formed so that a loop inductance, which is an L component, and a self capacitance, which is a C component, can be matched to achieve LC balance. Conventionally, LC balance is achieved using a transmission line structure such as a microstrip, a strip-line, a coplanar waveguide, etc.
However, LC balance according to conventional techniques inevitably increases the number of metal wiring layers of a printed circuit board used in the semiconductor devices and consumer electronics or the area of the printed circuit board. In contrast, in line with the recent development trend for semiconductor devices and consumer electronics, the number of metal wiring layers of a printed circuit board and/or the area of the printed circuit board should be reduced as much as possible. Accordingly, recent printed circuit boards include various interconnect wiring topologies besides a point-to-point connection. Therefore, more than three signal wirings may be arranged between power source wirings in an interconnect wiring on a coplanar printed circuit pattern.
Particularly, in the case of a printed circuit board of DRAM semiconductor packages having a board on chip (BOC) structure, all interconnect wirings are formed in a printed circuit board having a single-layer structure. Thus, signal wirings for command and address and power source wirings are formed adjacent to each other. Also, semiconductor packages using a printed circuit board having a multi-layer structure can also have a structure in which signal wirings for command and address and power source wirings can be formed adjacent to each other.
In this case, LC balance cannot be achieved only by adjusting the length of interconnect wirings because adjacent signal wirings and power source wirings affect each other during operation of the semiconductor package.
The present invention addresses these and other disadvantages of the conventional art.